-- EASE/HDL begin --------------------------------------------------------------
-- 
-- Architecture 'structure' of entity 'shift_reg'.
-- 
--------------------------------------------------------------------------------
-- 
-- Copy of the interface declaration:
-- 
--   port(
--     DCF_sig_dem   : in     std_logic;
--     Min_Begin_ebl : in     std_logic;
--     clk           : in     std_logic;
--     data_ebl      : out    std_logic;
--     dcf_data      : out    std_logic_vector(58 downto 0);
--     reset_n       : in     std_logic;
--     shift_ebl     : in     std_logic);
-- 
-- EASE/HDL end ----------------------------------------------------------------

architecture structure of shift_reg is

signal reg: std_logic_vector(58 downto 0); 
 
begin 
 
process(clk, reset_n) 
begin
	if(reset_n = '0')then
		reg <= (OTHERS=>'0');
	elsif(clk'EVENT AND clk = '1') then
	    if shift_ebl = '1' then 
	       reg <= reg(57 downto 0) & DCF_sig_dem;
	    end if;
	end if; 
end process; 
dcf_data <= reg; 

data_ebl <= Min_Begin_ebl;
 
end architecture structure ; -- of shift_reg

